1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular, a static random access memory device.
2. Description of the Related Art
FIG. 4 is a circuit diagram of a common conventional static random access memory (SRAM) cell.
The SRAM cell has a pair of driver transistors ND1 and ND2, which are NMOS transistors, a pair of load transistors PL1 and PL2, which are PMOS transistors, and a pair of access transistors NA1 and NA2, which are NMOS transistors.
Source electrodes of the driver transistors ND1 and ND2 are both connected to a ground (GND). Source electrodes of the load transistors PL1 and PL2 are both connected to a power supply VDD. A drain electrode of the driver transistor ND1 is connected to a drain electrode of the load transistor PL1. This connection point will hereinafter be referred to as “node 1”. A drain electrode of the driver transistor ND2 is connected to a drain electrode of the load transistor PL2. This connection point will hereinafter be referred to as “node 2”. A gate electrode of the driver transistor ND1 and a gate electrode of the load transistor PL1 are both connected to the node 2. A gate electrode of the driver transistor ND2 and a gate electrode of the load transistor PL2 are both connected to the node 1. A COMS inverter that includes the driver transistor ND1 and the load transistor PL1 and a CMOS inverter that includes the driver transistor ND2 and the load transistor PL2 constitute a latch circuit. One of source and drain electrodes of the access transistor NA1 is connected to the node 1 and the other is connected to a bit line True. One of source and drain electrodes of the access transistor NA2 is connected to the node 2 and the other is connected to a bit line Bar. Gate electrodes of the access transistors NA1 and NA2 are both connected to a word line.
The SRAM cell accomplishes high-speed and stable operation by usually setting the current driving ability ratio of the access transistors NA1 and NA2, which are activated by the word line, and the driver transistors ND1 and ND2, which constitute the latch portion, to approximately 1:3, and setting the current driving ability of the load transistors PL1 and PL2, which constitute the latch portion, equal to or lower than that of the access transistors NA1 and NA2.
The static noise margin, which is an indicator of the stability of data stored in a memory cell, is improved by setting the current driving ability of the load transistors PL1 and PL2 greater than that of the driver transistors ND1 and ND2.
However, setting the current driving ability of the load transistors PL1 and PL2 greater than that of the driver transistors ND1 and ND2 increases the ability of the nodes to keep to High and makes the discharging of the nodes (the reversal from High to Low) difficult in data write, which means less write margin.
In short, the static noise margin and the write margin have a trade-off relationship, and improving the two simultaneously is not easy.
FIG. 5 is a structural diagram of an SRAM cell with an improved statistic noise margin which is disclosed in JP 2006-066588 A.
The SRAM cell has a pair of driver transistors 11 and 12, which are NMOS transistors, a pair of load transistors 13 and 14, which are PMOS transistors, and a pair of access transistors 15 and 16, which are NMOS transistors.
Source electrodes of the driver transistors 11 and 12 are both connected to a ground (GND). Source electrodes of the load transistors 13 and 14 are both connected to a power supply VDD. A drain electrode of the driver transistor 11 is connected to a drain electrode of the load transistor 13 and to a drain electrode of the access transistor 15. This connection point will hereinafter be referred to as “node N1”. A source electrode of the access transistor 15 is connected to a bit line 18 and its gate electrode is connected to a word line 17. A drain electrode of the driver transistor 12 is connected to a drain electrode of the load transistor 14 and to a drain electrode of the access transistor 16. This connection point will hereinafter be referred to as “node N2”. A source electrode of the access transistor 16 is connected to an inverted bit line 19 and its gate electrode is connected to the word line 17. A gate electrode of the driver transistor 11 and a gate electrode of the load transistor 13 are both connected to the node N2. Agate electrode of the driver transistor 12 and a gate electrode of the load transistor 14 are both connected to the node N1.
The SRAM memory cell shown in FIG. 5 has a bulk type structure in which the bit line 18 is connected to an well of the load transistor 14 and the inverted bit line 19 is connected to an well of the load transistor 13. The node N1 is at the L level whereas the node N2 is at the H level. In data read, the bit line 18 and the inverted bit line 19 are precharged to the H level. The rise to the H level of the word line 17 causes a column current to flow in the driver transistor 11. When the electric potential of the bit line 18 changes to the L level, the electric potential of the well of the load transistor 14 concurrently changes to the L level. This prevents the electric potential of the node N2 from dropping much from the H level when the current driving ability of the load transistor 14 is improved and noise or the like causes a rise in electric potential of the node N1, which is accompanied by a slight on operation of the driver transistor 12. Accordingly, the electric potential difference between the bit lines 18 and 19 can be read and a malfunction in data read is avoided.
An analysis by the inventors of the present invention, however, has revealed the following:
To build the conventional memory cell having the circuit structure of FIG. 5 from silicon, the wells of the load transistors 13 and 14 which are PMOS transistors have to be separated because of their differing electric potentials. Since transistors are generally formed on a P-type silicon substrate, the well separation requires separating N wells from each other. The N wells need to be separated at a minimum distance that does not cause a short-circuit between the N wells even when the separated N wells have different electric potentials. This presents a problem in that the area of the SRAM cell is greatly increased.
There is another type of SRAM in which a precharge transistor connected to a pair of bit lines at non-selected addresses is kept on during read operation in order to speed up the read operation by eliminating the time for precharging for the next data read. The static noise margin of this type of SRAM cannot be improved with the SRAM cell structure disclosed in JP 2006-066588 A. This is because the electric potential of the bit lines in the SRAM cell at non-selected addresses does not change to the L level and accordingly the well electric potential of the load transistor does not change to the L level, which means no improvement in current driving ability.
The goal to be accomplished is therefore to increase the static noise margin and the write margin both at the same time while avoiding a significant increase in cell area of a static semiconductor memory device.